An example conventional fabricating process using a self-aligned silicidation technique (salicide transistor technique) is shown in FIGS. 7(a) through 7(e), which is disclosed in a report of K. Tsukamoto, T. Okamoto, M.
Shimizu, T. Matsukawa, and H. Harada, page 47 of "Extended Abstracts 16th (1984 International) Conference on Solid State Devices and Materials, Kobe, 1984", Business Center for Academic Societies Japan, Tokyo, 1984.
As shown in FIG. 7(a), a field oxide film 402, a gate oxide film 403, and a gate electrode 404 made of polysilicon whose sidewalls are covered with dielectric films 405 are formed on a silicon semiconductor substrate (hereinafter, referred to as Si-substrate) 401. Note that phosphorous is diffused into the polysilicon before patterning the gate electrode to dope an impurity into the gate electrode 404.
Next, as shown in FIG. 7(b), after an oxide film 406 is deposited, high-concentrated impurity ions are doped into the Si-substrate 401 where source and drain regions 407 will be made through the oxide film 406 using a photoresist mask. The impurity ions referred herein are, for example, arsenic ions in case of an n-channel and boron ions in case of a p-channel. Then, the Si-substrate 401 is subject to thermal annealing, for example, at 900.degree. C. for 30 minutes in nitrogen atmosphere to activate the impurity ions. As a result, the source and drain regions 407 are made in the Si-substrate 401.
Next, as shown in FIG. 7(c), after the oxide film 406 is removed from the source and drain regions 407 and gate electrode 404 with a solution or the like containing hydrofluoric acid, a titanium film 408 is sputter-deposited in argon atmosphere.
Next, as shown in FIG. 7(d), the Si-substrate 401 is subject to a first RTA (Rapid Thermal Annealing) at 675.degree. C. for about 20 seconds in nitrogen atmosphere to let silicon of the source and drain regions 407 and gate electrode 404 react with titanium. As a result, a titanium silicide film 410 having a metastable stoichiometric TiSi.sub.2 C49 crystal structure is formed. At this point, the surface of the titanium film 408 turns into a titanium nitride film 409.
Next, as shown in FIG. 7(e), after an unreacted portion of the titanium film 408 and the titanium nitride film 409 resulted from the first RTA are selectively etched off with a mixed solution of sulfuric acid and aqueous hydrogen peroxide, the Si-substrate 401 is subject to a second RTA at 800.degree. C. for about 20 seconds in nitrogen atmosphere to let the titanium silicide film 410 transform to a titanium silicide film having a stable stoichiometric TiSi.sub.2 C54 crystal structure.
However, oxygen or impurities interfere with the silicidation reaction in the above conventional semiconductor device fabricating process, and the resulting semiconductor device has problems, such as an increase in the junction leakage current and being more vulnerable to the short-channel effects.
To be more specific, when a CMOS device is fabricated by the conventional fabricating process, the Si-substrate is masked by a photoresist to dope the donor and the acceptor into their respective desired regions. Therefore, the oxide film 406 is a must in preventing contamination of the Si-substrate 401 by the physical contact to the photoresist containing a great amount of heavy metal during the ion implantation. This is the reason why the impurity ion implantation is carried out through the oxide film 406 in the conventional fabricating process. However, the knock-on oxygen inevitably caused by the impurity ion implantation always accelerates the penetration of oxygen into silicon. The adverse effect of such knocked-on oxygen is obvious especially when heavy ions are doped. Also, the knocked-on oxygen serves as the center of the deeper level recombination, and it undesirably increases the junction leakage current. These problems become more serious in the silicidation, which will be described below.
Additionally, during the wet step (cleaning followed by resist coating) for the patterning in the convectional gate electrode fabricating process, the polysilicon film, which will be made into the gate electrode, is deposited and open to air. Then, the wafer is transported for the following step while the surface of the polysilicon film is open to air. Thus, oxygen penetrates far deep into the polysilicon film along the crystal grain boundary from the surface. Once oxygen has penetrated into the polysilicon film, it can not be removed by, for example, the cleaning treatment (hydrofluoric acid treatment) before the silicidation.
Therefore, the adverse effect of such oxygen can not be eliminated in the silicidation reaction, and the 4-element (titanium-silicon-impurity-oxygen) silicidation reaction takes place. In this case, the impurity and oxygen interfere with the silicidation reaction, and oxides, such as SiO.sub.2, are produced predominately around the grain boundary of TiSi.sub.2. This increases the sheet resistivity and deteriorates the heat resistance.
Deterioration of the heat resistance, in particular, accelerates the agglomeration of the TiSi.sub.2 film during the post-silicidation thermal annealing, and there occurs a further problem if a film of a line narrower than the grain size of TiSi.sub.2 is subject to silicidation. Incidentally, recrystalization of metal usually becomes most apparent at a 0.6-time melting point (Tm) in absolute temperature. In case of TiSi.sub.2, for example, the melting point (Tm) is 1540.degree. C. and 0.6 Tm yields 815.degree. C. Thus, when a thermal annealing is carried out at 800.degree. C. or higher in the inter-layer reflowing step, or the silicidation is carried out through a rapid thermal annealing (RTA) at 900.degree. C. or higher, the TiSi.sub.2 film containing SiO.sub.2 and hence rendering poor heat resistance agglomerates SiO.sub.2 along the grain boundary due to the surface free energy of TiSi.sub.2. The TiSi.sub.2 film agglomerating SiO.sub.2 is disconnected in some portions, and is no longer able to serve as a silicidated line of low resistance. Particularly, when a gate electrode of a line narrower than the grain size of TiSi.sub.2 is subject to silicidation, the agglomeration occurs more readily compared with a gate electrode of a wider line, and the agglomerated SiO.sub.2 is highly likely to disconnect the line thoroughly. Therefore, the sheet resistivity increases up to substantially the same level as a non-silicidated line. Further, since Ti atoms diffuse through silicon during the agglomeration, the junction leakage current increases in the source and drain regions due to the damages to the junction and the gate oxide film of the gate electrode becomes less reliable. The agglomeration can be inhibited by lowering the temperature of the RTA during silicidation, for example, to 900.degree. C. or lower; however, in this case, it becomes difficult to turn the crystal structure of TiSi.sub.2 from C49 to C54, thereby raising the sheet resistivity of the titanium silicide film drastically. Thus, it is difficult to form a satisfactory titanium silicide film through the 4-element silicidation reaction, particularly in case of a narrower line. Although, the line width of a typical gate electrode is reduced to 0.25 .mu.m, there has been an increasing need for a gate electrode of a narrower line. Thus, problems as to keeping the heat resistance high (preventing agglomeration) and resistance low must be solved to fabricate a gate electrode of a narrower line.
As previously mentioned, the source and drain regions are formed by the ion implantation through the oxide film, and for this reason, the knocked-on oxygen serves as the center of the deeper-level recombination and undesirably increases the junction leakage current. Moreover, the silicidation causes a further rise in the junction leakage current.
In addition, as is disclosed in page 381, Proc. 1st Int. Symp. ULSI Science and Technology, Philadelphia, 1987, D. Moy, S. Basavaiah, H. Protschka, L. K. Wang, F. D'Heurle, J. Wetzel, S. Brodsky, and R. Volant, Electrochemical Society, Pennington, 1987, it is known that silicidating an n-type semiconductor (silicon doped with arsenic through the ion implantation) is quite difficult compared with a p-type semiconductor (silicon doped with boron through the ion implantation).
To be more specific, compared with the p-type semiconductor, the silicidation reaction in the n-type semiconductor is interfered with and hence the sheet resistivity increases while the heat resistance deteriorates (the silicide film agglomerates during the high thermal annealing). It remains unclear why there is such a difference in silicidation between the n-type semiconductor and p-type semiconductor, and using different ion seeds is assumed to be a major reason.
Further, in the conventional CMOS fabricating process, both the n-channel and p-channel are annealed simultaneously to activate the impurities doped therein. Thus, if the annealing conditions are optimized to reduce the junction leakage current in the n-channel side, the source-drain junction in the other p-channel side deepens because boron has a larger diffusing coefficient through silicon than that of arsenic. As a result, the short-channel effects become apparent in the p-channel side. Whereas if the annealing conditions are optimized to reduce the junction leakage current in the p-channel side, the crystalline quality will not be fully recovered in the other n-channel side because arsenic ions, which are heavier than boron ions, cause considerable damage during the ion implantation. As a result, the junction leakage current increases in the n-channel side.
The conventional semiconductor device has the above-explained problems and a semiconductor device capable of eliminating all of these problems has not been proposed yet.